Prediction of Protein Coding Regions on a Programmable Vliw Architecture

نویسندگان

  • Adeel Yusuf
  • Dawood Khan
چکیده

Gene annotation is by nature a computationally intensive problem, as it needs to process huge data size of DNA sequences. This forces the need to look for alternate ways of implementing algorithms to predict exons. The paper presents a hardware-based approach in which a Digital Signal Processor is programmed to compute the computationally expensive part of the algorithm. The processor effectively exploits the 3-periodicity property exhibited by protein coding regions and indicates their presence in the sequence. Experimental results show superior performance when compared with implementation on a general purpose Intel processor for evaluating exons from DNA. This PCI pluggable card offers a great utility to scientists and engineers actively involved in indexing DNA sequences.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A High Performance VLIW Processor for Finite Field Arithmetic

Finite field arithmetic forms the mathematical basis for a variety of applications from the area of cryptography and coding. For finite fields of large extension degrees (as for cryptography), arithmetic operations are computation intensive and require dedicated hardware support under given timing constraints. We present a new architecture of a high performance VLIW processor that can perform b...

متن کامل

Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA

FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This Processor Architecture is based on parallel processing in which more than one instruction is executed in parallel. This architecture is used to increase the instruction throughpu...

متن کامل

An Efficient Algorithm for Output Coding in Pal Based Cplds (TECHNICAL NOTE)

One of the approaches used to partition inputs consists in modifying and limiting the input set using an external transcoder. This method is strictly related to output coding. This paper presents an optimal output coding in PAL-based programmable transcoders. The algorithm can be used to implement circuits in PAL-based CPLDs.

متن کامل

A low-power programmable DSP core architecture for 3G mobile terminals

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless commu...

متن کامل

Fig. 1: Mpeg-4 Coding Scheme

A programmable processor architecture for MPEG-4 video is proposed, that can serve as a coprocessor module in MPEG-4 decoder systems. It consists of a 64-bit dual-issue VLIW macroblock engine, a separate RISC core for bitstream parsing and system processing, and an autonomous I/O processor. A separate DSP is used for MPEG audio support. The architecture is fully programmable and supports parall...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2006